Junior and Senior Verification Engineers
Job Description
Our client, is searching for Junior and Senior Verification Engineersto join their business in
Romania.
Job Description:
Our Romania based team is now looking to recruit ASIC/IP Design Verification Engineer to join our team. You will be part of the RTL verification team, working closely with the RTL Design team to create, test and deploy high performance IP cores for Memory Subsystems.
Responsibilities:
Understand the functionality of Memory Subsystem IP Cores and define strategies for testing
Implement verification environment testing new IP Cores
Define quality metrics for verification and measure the results
Define and implement reusable components for verification
Documents the verification efforts and results
Requirements:
Studies in Electronic Engineering, Computer Science or equivalent
Experience using System Verilog verification language or similar
Experience in using verification methodologies, proficient using UVM
Good understanding of Verilog/VHDL and the ability to debug digital circuits on RTL and gate level.
Experience in version control tools and methodologies
Basic experience in C, C++ language
Good scripting skills (Perl, Python, Make or similar)
Good communication, strong analytical skills, team oriented, initiative
Good written and spoken English
Additional Skills (would Be Added Advantage)
Previous experience with complex standards such as DDR, Ethernet, PCIe, USB
Fii primul, care se va înregistra la oferta de muncă respectivă!
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